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A Step-By-Step Methodical Approach for Efficient Mixed-Language IP Integration   Featured
Publication: Design & Reuse
Contributor: Mentor Graphics Corp.
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March 22, 2010 -- IP reuse has long been touted as one of the key factors in enabling development of today's complex SOC designs. The concept of reuse seems simple and easy in theory, but there are a number of obstacles that design and verification teams must address to be successful, especially in the case of commercial IP cores. One of the significant barriers to IP reuse today is the wide variety of design languages used in IP.

Often designers are not aware of various mixed-language design integration options. Other times the knowledge on various options is available, but it is difficult for a user to choose the best suitable option based on their mixed language design scenario. This difficulty in mixed-language IP integration and reuse often leads to finding issues late during the design cycle, which impacts the overall productivity.

This article provides a comprehensive methodology that highlights the best practices for mixed-language design integration and automatically comes up with an option for designers to select the optimal method for integration. There are broadly five ways of making mixed-language connections. Pros and cons of each of these approaches and their comparison is described in terms of the usage scenarios, performance implications of using one versus the other, delta cycle value update concerns, and more. A step-by-step guideline based on decision-making trees that designers can follow to help them decide which approach best suits their particular mixed-language integration scenario is also discussed.

By Pankaj Singh and Gaurav Kumar Verma. (Singh is with Infineon Technologies and Verma is with Mentor Graphics Corp.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Design & Reuse website.

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Mentor Graphics Corp.
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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, design reuse, Mentor Graphics, Design & Reuse,
596/30972 3/22/2010 2645 236


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