April 13, 2010 -- By increasing their usability, applicability, and quality of results (QoR), high-level synthesis (HLS) solutions are proving that they can fulfill their initial promise. One day, not using HLS will be like not using RTL synthesis today. And that day will not be long. Many hardware engineers are already changing how they get things done by making HLS an integral part of their design methodology.
What they've discovered is that the benefits of HLS not only profit the companies that adopt it; but hardware engineers who acquire the HLS skills to work at both the ESL and RTL are more valued and sought after than their counterparts, especially as increasingly complex designs and market pressures grant HLS-savvy engineers an undisputed competitive advantage. HLS makes their jobs easier and more productive because it shortens the time to verified, production-ready RTL.
However, the pool of potential HLS users is larger than those who have adopted it. Why haven't all hardware engineers gotten on board the HLS gravy train? As is typical when we fundamentally change the way we do things, there are technological, practical, and psychological hurdles. Development of the associated tools and methodologies is largely a response to the first two, followed by the removal of the last hurdle as the engineering community begins to perceive that these things have indeed reached maturity.
There are three clear signs that at least some HLS tools and methodologies have reached maturity.
- A shortened time to first results.
- A broader application scope.
- Improved quality of results.
Already, users of HLS are making it known that this is a technology with street cred. And now that tools like Catapult C Synthesis offer mixed language support and full-chip synthesis, HLS has truly arrived as a capable technology, proving itself with production quality results among a growing community of users.
By Shawn McCloud. (McCloud is the Product Line Director for the Mentor Graphics Corp. high-level synthesis technology.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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