Page loading . . .

  
 You are at: The item(s) you requested.Sunday, May 19, 2013
Implementing Different Power Features In an IP  
Publication: Design & Reuse
Contributor: Synopsys, Inc.
 Printer friendly
 E-Mail Item URL

April 29, 2010 -- This article focuses on methods of defining power features based on the functionality of the design. It explains how power states can be defined and how different power features can be implemented for different power states in order to achieve higher power savings. A USB IP is used as an example throughout although the power features explained are generic and they can be used as a good reference for implementation in both data path and connectivity IPs.

This article covers the following topics:

  • Need for power optimization in an IP.
  • Defining power states for an IP.
  • Introduction to power features.
  • Verification of power features.
  • Defining power states in a USB IP.
  • Implementing features for power states.

By Sayandeep Nag, B.U. Chandrashekar and K.D. Prathima. (Nag and Chandrashekar are with Synopsys, Bangalore, India; Prathima is with the Manipal Center for Information Science, Manipal, India.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Design & Reuse website.

Read more about
Synopsys, Inc.
on SOCcentral.com

Keywords: ASICs, ASIC design, IP, intellectual property, cores, Universal Serial Bus, USB, Design & Reuse, Synopsys,
596/31271 4/29/2010 1995 167


Designer's Mall
0.15625



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.25