June 10, 2010 -- Accurate power grid analysis of 65-nm and smaller chips is becoming increasingly important to ensure reliable operation of devices in the field. Re-spins due to on-chip power-distribution issues are expensive and time-consuming and can lead to lost business opportunities. However, power grid analysis of complex deep-submicron SOCs (systems on chips) with digital, analog, and third-party IP (intellectual-property) blocks can be a difficult task. The task becomes even more daunting when you couple it with looking at variations over multiple corners, as well as between static and dynamic analyses. This article explores a power-grid-analysis flow on a high-performance, 65-nm SOC graphics chip design and compares the results of different analysis types and corners.

Ravi Poddar, Ph.D., and Ted Sun. (Poddar is the director of CAD for the Design Automation Group at Integrated Device Technology and Sun is the staff CAD engineer in the Design Automation Group at Integrated Device Technology.)