June 10, 2010 -- In the last few decades the semiconductor industry has successfully and dramatically improved the capabilities of electronics, particularly in the areas of speed and power consumption. Each new technology node has brought the potential for even faster speed at even lower power levels.
While Moore’s Law has always been theoretically faithful in terms of its continued march forward with transistor density, the complexity of designing to advanced geometries flirting with atomic sizes has resulted in a frustrating paradox: it is not easy to take full advantage of the new nodes because high variations require design margins that limit the intrinsic technology potential.
Today, design engineers must evaluate trade-offs between power and speed, typically compromising on one or the other. Yet, in an uncompromising consumer market that demands both higher performance AND longer battery life, what to “leave on the table” is a difficult and painstaking decision.
Designers have long sought the Holy Grail of a solution to maximize the performance vs. power trade-off. Fast designs that meet stringent power requirements. The ying and yang of complex IC design.
One such approach that has been looked at for many years as having great promise is asynchronous or clockless design technology. This technique has always seemed to be academically and conceptually a very viable method, but various attempts at making it a commercial success have never gotten traction.
By Alban d'Halluin. (d'Halluin is director of product marketing at Tiempo.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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