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ESL Synthesis: Tips for Implementing a Viable ESL-Synthesis Flow  
Publication: EDN Magazine
Contributor: Gary Smith EDA
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July 15, 2010 -- As with any other technology, ESL invites squabbling among vendor technologists and early adopters about the goal of synthesis. One goal seems to capture the key aspects from a user perspective: An ESL-synthesis platform enables high-level specification, optimization, and verification and automatically leads to verifiable RTL code with result quality comparable to that of manual methods.

By Nancy Wu. (Wu is with Gary Smith Consulting.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EDN Magazine website.

Read more about
Gary Smith EDA
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, electronic system level design, ESL, synthesis, EDN Magazine, Gary Smith EDA,
596/31868 7/30/2010 1735 259
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