July 29, 2010 -- As microprocessor designs have grown considerably in complexity, the use of hand-written directed tests in verification has dwindled. Automated random test generators that cover the stimulus space more efficiently have emerged in their place. These random test generators create microcode test sequences, emphasizing the distribution of stimuli across all meaningful values for opcodes and other instruction attributes. Traditional methods randomize instruction fields sequentially, which often results in verbose, redundant code and limited control over distributions.

In this article, we explore using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys constraint solver. We present and analyze the method and discuss its effectiveness in today's verification environment.

The constraint language constructs in the SystemVerilog language provide a clean, concise format for describing microcode instructions in terms of their possible attribute combinations and allow precise control over the distribution of values for each individual field. An initial test generator prototype was implemented using a single class, in which constraints for all opcodes were defined. This early design was able to overcome all the aforementioned flaws of sequential randomization methods.

Using an object-oriented approach, a base class was then implemented with global constraints pertaining to all opcodes. Sub-classes were derived to define groups of related opcodes with similar constraints. By partitioning the constraints hierarchically into smaller groups of opcodes, the memory requirements were drastically reduced, which increased performance.

By Gregory Tang, Rajat Bahl, Alex Wakefield and Padmaraj Ramachandran. (Tang and Bahl are with AMD, Inc.; Wakefield and Ramachandran qre with Synopsys, Inc.)