| IP Re-Engineering and Design Methodology | Publication: Design & Reuse Contributor: MindTree, Ltd.
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July 6, 2010 -- Today SOCs are becoming increasingly complex with hundreds of IPs being reused, integrated and further translated into millions of transistors in the design process. Each IP used in these SOCs evolves from one stage to another stage during the design cycle. The IP after a certain stage will undergo changes for the new requirements or to fit the design environment changes or due to known bugs (including silicon bugs) discovered during the validation.
In the current trend an IP can be used in multiple SOCs and hence there is a need for the IP to be configurable, robust and support multiple projects (requirements) with minimal effort from the IP user to modify the IP. To cater to these changing requirements a new methodology to re-engineer IPs has been developed to enhance, sustain and maintain IPs.
By B. Akash Apasangi and Venugopal Nallamalli. (Apasangi and Nallamalli are with MindTree, Ltd.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Design & Reuse website.
Read more about MindTree, Ltd. on SOCcentral.com |
| | Keywords: FPGAs, field programmable gateEDA, EDA tools, electronic design automation, arrays, FPGA design, ASICs, ASIC design, IP, intellectual property, cores, Design & Reuse, MindTree,
| | 596/31877 7/29/2010 2625 219 | |
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| | 0.1601563 |
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