September 9, 2010 -- Discovering the last unrealized power reduction imagePower has become one of the most important design criteria for almost all design projects, and the industry, in response, has invested a lot of effort to address this challenge. Consequently, we have seen a plethora of low-power design techniques and new technologies emerge. Some of these techniques are relatively easy to adopt. For example, clock gating and multiple-threshold-voltage cells have become mainstream design practices because they are effective. In addition, EDA tools can automate their implementation. Some techniques, on the other hand, require more planning. For example, design engineers can group SOC (system-on-chip) circuits into multiple blocks so that they can power down some blocks or operate them at reduced frequencies or voltages when operating conditions allow it. Although these more advanced techniques take more deliberate effort to implement, design engineers are increasingly employing them to meet the more stringent power requirements in next-generation chips.

When applying low-power design techniques, design engineers typically concentrate on only the few modules, such as embedded processors and on-chip memories, that consume more power than the other blocks. Although this focus is necessary, it is incomplete. Engineers may often overlook the fact that many low-power-consuming blocks frequently have a greater impact on energy consumption than their power- consumption number suggests. If you correctly plan a chip's power-management strategy, the power-consumption profile and energy-consumption profile should not correlate closely. You should keep the active period of the high-power-consuming modules as short as possible. The modules that remain powered for a long time should not consume too much power. Even though these modules consume less power than other blocks, they consume a higher proportion of energy once you factor in their extended active time.

By Jay Chiang. (Chiang is with Synopsys, Inc.)