November 4, 2010 -- Power dissipation has become a key constraint for the design of today's complex chips. Minimizing power dissipation is essential for battery-powered portable devices, as well as for reducing cooling requirements for non-portable systems. Such minimization requires active power management built into a device.

In a system-on-chip (SOC) design with active power management, various subsystems can be independently powered up or down, and/or powered at different voltage levels. It is important to verify that the SOC works correctly under active power management.

When a given subsystem is turned off, its state will be lost, unless some or all of the state is explicitly retained during power down. When that subsystem is powered up again, it must either be reset, or it must restore its previous state from the retained state, or some combination thereof. When a subsystem is powered down, it must not interfere with the normal operation of the rest of the SOC.

is essential to verify the operation of a design under active power management, including the power management architecture, state retention and restoration of subsystems when powered down, and the interaction of subsystems in various power states. In this article, we summarize the challenges of power aware verification and describe the use of IEEE 1801-2009 Unified Power Format (UPF) to define power management architecture. We outline the requirements and essential coverage goals for verifying a power-managed ARM-based SOC design.

Ping Yeung, Ph.D.and Erich Marschner. (Yeung is the Principal Engineer in the 0-In Business Unit of Mentor Graphics Corp. and Marschner is Verification Solutions Manager at Mentor Graphics Corp.)