Page loading . . .

  
 You are at: The item(s) you requested.Wednesday, June 19, 2013
Parametric yield: Do You Know What You Miss?  
Publication: EE Times EDA Designline
Contributor: InfiniScale
 Printer friendly
 E-Mail Item URL

November 10, 2010 -- Since moving to sub 65-nm technologies, pre-defined corners (PDC) verification has attained its limits. The number of corners to verify has become huge with always the possibility of over-design. The worst is that these corners cannot guarantee the design. Some corners could fall inside the process parameters space while others do not really need to be tested.

In this context, EDA has started looking for solutions for this new and key concern. Many solutions have been developed on the back-end side to reduce variability, analyze yield or enhance it. These solutions, although very useful, were not sufficient. Another effort at design level has been made concerning parametric yield. This is thoroughly developed in this article.

Today, the EDA market offers tools based on the following different approaches:
  • Manual sizing and PDC.
  • Manual sizing and simulator-based analysis.
  • Simulator-based sizing and yield optimization.
  • Model-based sizing and yield optimization.

From the different approaches, two main workflows appear:
  • Analysis flow where the designer does the sizing manually and then the verification by PDC or a lot of Monte Carlo based on a simulator or a model.
  • Optimization flow where the designer trusts the tool to do the yield estimation and optimization. In this case, simulator-based tools generally need a good design point in order to be able to enhance the yield. By contrast, model-based tools can provide a global exploration of the design and thus find the point that best yields. Nevertheless, modeling and model-based approach is a new methodology that needs to be educated!


By Yoann Courant and Firas Mohamed. (Mohamed is founder, chairman of the board and CEO of Infiniscale SA and Courant is cofounder and R&D director of Infiniscale SA.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
InfiniScale
on SOCcentral.com

Keywords: ASICs, ASIC design, custom IC design, EDA, EDA tools, electronic design automation, design for manufacturing, design-for-manufacturing, DFM, design for yield, design-for-yield, DFY, EE Times EDA Designline, InfiniScale,
596/32631 11/10/2010 999 154
Designer's Mall
4th Of July countdown banner
0.15625



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.234375