October 29, 2010 -- With traditional chip-fabrication materials reaching the limits of miniaturization, how can we further miniaturize future chips? Traditionally, chips have been designed mostly on the x and y axes (flat), ignoring the z (vertical) axis. 3D packaging is a recent innovation that stacks prepackaged chip die one atop the other, also integrating the necessary passive devices, before securing them into a package for protection.
By Chris Sellathamby, Ph.D. (Sellathamby is with Scanimetrics, Inc.)
This brief introduction has been excerpted from the original copyrighted article.