January 12, 2011 -- To be competitive, IC designs that power data centers and mobile handheld devices not only need to control and reduce their overall power consumption, but also must excel in other metrics such as performance per watt or performance per Gbps. Depending on the application (server, networking, 3D graphics, handheld device, etc.), the specific area of power consumption to be addressed for a particular design can be different. For example, in a processor or SoC for a handheld device, very low levels of operational and standby power targets are critical design criteria.

Several techniques and methodologies have emerged to target low power design needs, but they do not contribute to reducing the operational or standby power numbers. They either have a marginal impact, or come too late in the design cycle. This approach towards power is usually ad hoc and is superseded by timing, area and routing considerations.

To meet the challenges, a new design methodology that considers power as a design target should be adopted and followed through the entire design chain; starting from the micro-architecture definition and continuing through the RTL design period all the way to physical implementation and sign-off. By employing this process early, you can identify areas of opportunity for power reduction and benefit from the freedom to implement circuit changes that will help in power reduction.

In addition, power consumed by the chip (at block or full-chip level), should be tracked through the entire design process to ensure convergence on the power goals set for the design. However, to be successful this methodology must go hand-in-hand with other design targets including performance, area, noise and timing. So the design changes proposed by the low-power methodology should be simulated and reviewed within the context of these other important design requirements. A comprehensive holistic approach to low power design that analyzes power throughout the entire process; identifying and implementing changes in the circuit that realize power reduction with consideration for other design goals, is a "design for power" methodology.

By Aveek Sarkar. (Sarkar is Vice President of Product Engineering and Support at Apache Design Solutions, Inc.)