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Using Co-Design to Optimize System Interconnect Paths  
Publication: EE Times Embedded
Contributor: Cadence Design Systems, Inc.
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January 16, 2011 -- Since the dawn of semiconductors, the dies, the packages, and the boards they reside on have typically been designed by different teams that focus their expertise between predefined boundaries. Most have seen those flows where the die design gets thrown over the wall to the package designer, who then designs the package and throws the package footprint over the wall for the printed circuit board (PCB) designer to incorporate into the board design.

Today, memory interfaces have single-ended data rates in the 1GHz-plus range, and serial links are running upwards of 10Gbps. The "throw-it-over-the-wall approach" has become completely ineffective. A precise design, analysis, and rules-based control of each of these signals is required at the die, package, and PCB level. The analysis and optimization performed on each one of these interconnection levels must be done in a global context.

By Real Pomerleau, Stephen Scearce, and Tom Whipple. (Pomerleau is a technical lead engineer in the Systems and Silicon Engineering High Speed Design team at Cisco Systems, Inc.; Scearce is the manager of the Systems and Silicon Engineering High Speed Design team at Cisco Systems; and Whipple is currently a Product Engineering Architect at Cadence Design Systems, Inc.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the EE Times Embedded website.

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Cadence Design Systems, Inc.

Keywords: PCB design, EDA, EDA tools, electronic design automation, packages, packaging, package design, PCBs, printed circuit boards, Cadence Design Systems, EE Times Embedded,
599/33026 1/16/2011 1746 306
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