| What Makes an Optimal SOC Verification Strategy | Publication: EE Times EDA Designline
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March 21, 2011 -- During the last decade, connected devices resulting from cross pollination of Internet and mobile phone technologies dominated the electronics world. Personalized products and services have penetrated our society so much that it is hard to imagine life in their absence. If "connectivity" was the buzz for a while, "intelligent connected solutions" will dominate the electronics world in this decade.
This intelligence comes from additional sensors which means more analog on the chip thereby complicating the SOCs further. Pressure from time-to-market limit the SOC design schedules, leaving minimal margin of error in the whole process. Verification claiming most part of the schedule becomes all the more critical.
A typical SOC design for a consumer electronic device will have blocks that can be broadly classified into processors, DSP cores, peripherals, memory controllers, layered bus architectures and analog components. An optimal SOC verification strategy should address all the challenges that would be encountered during the process of verification. It should include answers to these questions: what to verify, how to verify and "are we done?"
By Gaurav Jalan. (Jalan is with SmartPlay Technologies India Pvt., Ltd.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
| | Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, verification, system-on-chip, SoC, EE Times EDA Designline, SmartPlay Technologies,
| | 599/33519 3/21/2011 1174 155 | |
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| | 0.15625 |
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