April 7, 2011 -- One of the most popular topics for conference sessions lately has been the 3-D IC. Panels and papers cover a huge range of topics, but they come down to three questions: What is a 3-D IC, is it real, and what difference does it make? The question of definition is surprisingly loaded. At a recent panel, speakers divided the world of 3-D ICs into three categories.
The first category covers simply stacking up independently designed dice and bonding them together, such as the stack of flash and DRAM dice on the SOC (system-on-chip) die in your cell phone. In the stacking approach, all the dice are pretested standard parts, often simply wire-bonded together using their normal I/O bonding pads, sometimes with a silicon interposer to move signals around for the best wire-bonding layout.
The second category of 3-D ICs starts in the architectural-design phase of the system. Architects and IC designers partition the system according to the best technology in which to implement each block. Logic blocks might go into a 20-nm logic process; bulk memory, into a DRAM process; and I/Os and other AMS (analog/mixed-signal) blocks, into a large-geometry, higher-voltage process.
In the third category, which you could call true 3-D, designers place each cell not in a plane on one die but in the 3-D space they create by stacking many dice together. TSVs become just another element in the routing hierarchy.
By Ron Wilson, Editorial Director, .
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.