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Software Driven Verification  
Publication: Design & Reuse
Contributor: Synopsys, Inc.
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June 2, 2011 -- This article will discuss the changing landscape of verification caused by the increased importance of software for the success of chip design projects. With software determining an increasing amount of functionality, design teams are adopting virtual prototypes for early software development. Another use case for virtual prototypes is software driven verification, in which testbenches for verification of the hardware are executed in software running on transaction-level models of processors as part of virtual prototypes. This article also will illustrate the use cases of software for hardware verification across design and verification flows for chip-design.

By Achim Nohl and Frank Schirrmeister. (Both Nohl and Schirrmeister are with Synopsys, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Design & Reuse website.

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Synopsys, Inc.
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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, verification, testbenches, Synopsys, Design & Reuse
599/33990 6/2/2011 1214 145


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