SOCcentral: Virtual Modeling with Aldec and Imperas (Aldec, Inc. 34156)

You are at: The item(s) you requested.

Thursday, May 23, 2013

Virtual Modeling with Aldec and Imperas

Company: Aldec, Inc.

Printer friendly

E-Mail Item URL

Virtual platforms play a significant role in system level development, but they require the speed that emulation systems provide for hardware/ software co-verification. This white paper describes a high-performance virtual modeling solution achieved by integrating Aldec's Transaction Level Emulation System with Imperas' OVP (Open Virtual Platform) and OVPsim (OVP simulator). Hardware and software design teams are now able to simulate and debug virtual models of processors, memories and peripherals while the rest of the system resides in the emulator board running at MHz clock speeds.

Access the entire document on the Aldec, Inc. website.

E-mail Aldec, Inc. for more information.

Read more about
Aldec, Inc.
on SOCcentral.com

Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, emulators, emulation, transaction level modeling, transaction-level modeling, TLM, simulation, simulators, Aldec, Imperas, OVPsim (OVP simulator),

205/34156 6/24/2011 699 89

Add a comment or evaluation (anonymous postings will be deleted)

Designer's Mall

0.25

Search site for:
Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification

Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP

Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!

Mike Donlin
The Write Solution
Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL

Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search
SOC Design ASIC Design ASIC Verification FPGA Design CPLD Design PCB Design DSP Design RTOS Development Digital Design	Analog Design Mixed-Signal Design DFT DFM IC Packaging VHDL Verilog SystemC SystemVerilog