Page loading . . .

  
 You are at: The item(s) you requested.Thursday, June 20, 2013
Creating an SOC Virtual Platform for Embedded Software Development  
Publication: Electronic Design Magazine
Contributor: CircuitSutra Technologies Pvt, Ltd.
 Printer friendly
 E-Mail Item URL

June 28, 2011 -- Today's system-on-chip (SOC) designs incorporate various input-output capabilities and are multi-core systems with fast communication protocols. SOCs often incorporate various processing elements for multimedia and networking applications. The convergence of computing, communications, and multimedia data processing onto one chip pushes SOC complexity in two areas: SOC integration and software development.

To address SOC integration issues, the industry has been moving toward standardizing the IP core interfaces to achieve high reuse. The Open Core Protocol-International Partnership (OCP-IP) is a standards forum focusing on SOC integration concerns. OCP-IP defines a high-performance, SOC bus-independent interface between IP cores. This makes the IP core independent of the architecture and design of systems in which they are used.

SOC developers not only need to achieve high performance, but the product also must be flexible and programmable. As a result, SoCs are becoming software intensive. Software content on these SOCs comprises low-level firmware, device drivers, telecom/ communication stacks, operating system (OS) code, and application software, etc. Development and validation of so much software is a big challenge.

To address these software development challenges, the industry has been adopting more abstract simulation models, which can deliver enough performance and accuracy to enable software development to begin in parallel with chip development. The Open SystemC Initiative (OSCI) is a standards forum focusing on defining the standards for creating software models of SOC. SystemC is a standard language for modeling of SOC. OSCI TLM2.0 is a standard library for transaction-level modeling. OCP-IP has created an advanced modeling kit by extending OSCI TLM2.0 for the Open core protocol.

The OSCI and OCP-IP standards have the potential to address most of the challenges in current SOC designs. We at CircuitSutra have demonstrated the virtual platform by using the modeling standards from OCP-IP and OSCI.

Using the virtual platform for embedded software development instead of using an FPGA board provides several advantages. It allows hardware design and embedded software development to proceed in parallel, hence reducing the time to market for electronics product. It also provides more powerful debug features needed to develop and verify complex software for a multicore SOC.

This article discusses how to create an SOC virtual platform for embedded software development.

By Umesh Sisodia, Girish Verma, Ashwani Singh, Dheeraj Kaushik. (Sisodia is CEO at CircuitSutra Technologies; Verma serves CircuitSutra Technologies as a technical leader in the SOC modeling domain; Singh is a technical leader in the SOC modeling domain; and Kaushik works with CircuitSutra Technologies as a consultant in the SOC modeling domain.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Electronic Design Magazine website.

Read more about
CircuitSutra Technologies Pvt, Ltd.
on SOCcentral.com

Keywords: embedded system design, embedded systems, EDA, EDA tools, electronic design automation, software development tools, IP, intellectual property, cores, Electronic Design Magazine, CircuitSutra Technologies, system-on-chip, SoC,
599/34274 6/28/2011 1664 118
Designer's Mall
4th Of July countdown banner
0.15625



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.25