July 14, 2011 -- The desire to integrate more gates has driven two advances in CMOS-processing technology, enabling the integration of practical inductors in generic CMOS-logic processes. The first, the use of CMP (chemical-mechanical polishing), makes each layer in the interconnect stack more planar, allowing for many stacked metal layers. In 180-nm technology, which debuted in the late 1990s, the use of six metal layers became common. Recent process technologies at 65nm and smaller allow for 10 or more metal layers.

The increase in metal layers allows designers to put the inductors in the top metal layers, far above the silicon surface, reducing the parasitic capacitance and increasing the self-resonant frequency. The second advance, the use of copper interconnect, allows for lower series resistance and a higher Q factor because copper interconnect has a lower resistance than aluminum.

By Jeff Galloway and Andrew Cole. (Galloway is a co-founder of Silicon Creations and is responsible for analog IP (intellectual-property) design and development; Cole joined Silicon Creations in late 2010 and provides engineering leadership and sales support.)