| Averant Adds RTL and Gate-Level Combinational Equivalency Checker | | |
August 1, 2011 -- Averant, Inc. has announces the release of Solidify 5.4 which adds a fast combinational equivalency checker (CEC) and improved sequential equivalency checking (SEC).
When proving two designs are equivalent, a significant portion of the two designs are combinationally equivalent. A fast combinational equivalency checker (CEC) has been added to to catch such cases. In addition, the sequential equivalency checking (SEC) engines have been enhanced to provide speed-ups of several orders of magnitude in some cases, in addition to improved proving powers.
Release 5.4 also provides better SystemVerilog design support, speed-ups in formal engines, improved reset sequence guessing, improved SEC debugging, improved protocol checking, including ARM AMBA protocols, and bug fixes.
Availability
Release 5.4 is available immediately.
Go to the Averant, Inc. website to find additional information.
| E-mail Averant, Inc. for more information.
Read more about
Averant, Inc.
on SOCcentral.com |
| Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, formal verification, equivalence checking, SystemVerilog, Averant, Solidify,
| | 600/34384 8/2/2011 627 100 | |
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