|Publication: EE Times EDA Designline|
Contributor: Freescale Semiconductor, Inc.
July 25, 2011 -- As a designer, it is the general tendency to minimize skews and have a perfectly balanced clock tree. Zero skews are not always good for the design as it may result in very high dynamic power consumption as all the flops and buffers will be toggling at the same time. As technology is shrinking and frequency is increasing, the impact magnifies. Also minimizing skew comes at a very big cost of power, congestion and die area.
In this article we propose the optimal criteria for selection of skew number to minimize power, congestion and, at the same time without any compromise in timing across all the corners. By optimal selection of skew number we are able to reduce the clock power consumption by 15%, clock buffer count by over 30% and significant congestion reduction with similar timing summary across all the corners.
By Ravi Chhabra, Srijith Nair, and Ekta Gujral. (Chhabra is a Senior . Design Engineer at Freescale Semiconductors, Noida, India; Nair is a Senior Design Engineer at Freescale Semiconductors, Noida, India; and Gujral is an intern at Freescale Semiconductors, Noida, India.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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Freescale Semiconductor, Inc.
|Keywords: ASICs, ASIC design, embedded system design, embedded systems, computer system design, general-purpose computers, special-purpose computers, clocks, clocking, clock distribution, timing analysis, timing optimization, timing closure, EE Times EDA Designline, Freescale Semiconductor, |
|599/34413 7/25/2011 669 117|