August 6, 2011 -- Minimizing leakage power in systems-on-chip (SOCs) has become a major priority for designers because it increases drastically in submicron process technologies, becoming a major proportion of power usage. There are various design techniques to optimize dynamic power, such as power gating and dynamic voltage and frequency scaling (DVFS), but these require architectural changes that add to chip complexity, which you want to avoid in SOCs. Multiple voltage threshold (Multi-Vt) flow is the only technique that doesn't require changes to the SoC architecture; it depends instead on how judiciously the designer uses Low-Vt cells. Low-Vt cells have better timing but higher leakage power; High-Vt cells have lower leakage but worse timing.

The authors describe the use of a multi-threshold voltage (Multi-Vt) flow technique that does not require embedded SOC architecture changes and allows a designer to decide when to use Low-Vt cells, which have better timing but higher leakage power, and when to use High-Vt cells which have lower leakage but worse timing.

By Rajiv Mittal, Abhishek Mahajan and Sorabh Sachdeva. (Mittal is working with Freescale Semiconductor, Inc. as Staff Design Engineer; Mahajan and Sachdeva are Senior Design Engineers at Freescale Semiconductors, Noida, India.)