September 6, 2011 -- Altera Corp. today reached another milestone in the industry's roll-out of 28-nm FPGAs by announcing availability of the Stratix V GX FPGA Signal Integrity Development Kit, the first development kit featuring 28-nm FPGAs. The Stratix V GX FPGA Signal Integrity Development Kit provides a platform for measuring and evaluating transceiver link performance ranging from 600Mbps to 12.5Gbps.

The Stratix V GX FPGA Signal Integrity Development Kit features advanced equalization functions for the device's high-speed serial transceivers. Designers can perform real-world system analysis using on-board SMA and popular backplane connectors including Molex Impact and Amphenol XCede. These built-in high-speed backplane connectors are used to evaluate custom backplane performance and evaluate link BER. Users can also generate and check pseudo-random binary sequence (PRBS) patterns via a graphical user interface.

"To meet the ever increasing data rates and bandwidth requirements of today's high-end communications systems, it's essential for SerDes providers to invest in signal and power integrity in their silicon," said Dr. Eric Bogatin, Signal Integrity Evangelist with Bogatin Enterprises, a LeCroy Company. "Altera's Stratix V Transceiver Signal Integrity Development Kit provides an ideal vehicle to evaluate transceiver performance for customer applications and accelerate the development time for new designs."

The Stratix V FPGA Signal Integrity Development Kit lets users verify compliance with the most popular protocol standards today, including 10GbE, 10GBASE-KR, PCI Express (PCIe) Gen1, Gen2 and Gen3, Serial RapidIO, Gigabit Ethernet (GbE), 10 GbE XAUI, CEI-6G, CEI-11G, HD-SDI, Interlaken and Fiber Channel. The development kit features a Stratix V GX FPGA-based development board, a one-year license of Quartus II Software, design examples and access to Altera's MegaCore IP library including the Nios II Embedded Design Suite.

Availability and Pricing