Publication: Design & Reuse
Contributor: Mentor Graphics Corp.
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August 25, 2011 -- Transaction analysis and debug between multiple abstraction levels is now possible with current technology. This article will present an API and implementation for recording transactions from SystemC, C or C++, SystemVerilog, VHDL and Verilog. In addition, we'll discuss how to record transactions from existing RTL or gate-level designs.
By Rich Edelman. (Edelman is with Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Design & Reuse website.
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| | Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, SystemC, C/C++, SystemVerilog, VHDL, Verilog, transaction level modeling, transaction-level modeling, TLM, formal verification, electronic system level design, electronic system-level design, ESL, Design & Reuse, Mentor Graphics
| | 599/34661 8/25/2011 857 108 | |
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