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Managing IP Quality in the SOC Era Requires a Purpose-Built DM Approach  
Publication: Electronic Engineering Times (EE Times)
Contributor: Methodics LLC
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September 19, 2011 -- A modern SOC development project has a plethora of "moving parts." While there are many tools available to help verify, debug and otherwise manipulate IP, there has been a distinct lack of a solid design data-management system to address the specific needs of SOC designers in this type of dynamic environments.

As a result, IP use in general often suffers from a bad rap in terms of quality. The term IP quality has different meanings to different people, but in general terms it refers to 1) the functional correctness of the IP — does it work they way it is supposed to (i.e. bug free)"; and 2) does it do what I need it to do with respect to my design parameters — power, timing, area, etc.?

Developing and integrating quality IP by either or both of those definitions requires a system that can effectively track changes and input across the entire design team at the desktop level, provide real-time access to a wide range of meta data and quality information on IP, as well as keep project managers and other senior management informed on how the use of IP is impacting schedules, budgets and design resources. Without accurate and current quality metrics for dependent IP components designers are often forced to overdesign using pessimistic slack definitions, unrealistic size information, inaccurate power estimates, etc.

A system cognizant of the IP versions in a user's current context, with up-to-date metrics for dependent blocks, provides a truly collaborative and accurate development environment, which translates to reduced development cycles and cost,

By Simon Butler. (Butler is the CEO of Methodics LLC.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Electronic Engineering Times (EE Times) website.

Read more about
Methodics LLC
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, design management,
599/34754 9/19/2011 1392 98


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