September 8, 2011 -- Physical defects within ICs, such as shorts and opens, can occur during manufacturing at any step along the fabrication process because of the complexity of modern CMOS technology nodes. The conventional approach to test for these physical defects includes structural tests using classical fault models such as stuck-at (SA), bridging, and transition faults. This approach has efficiently addressed defects between standard cells and defects at input and output ports of library cells.
However, stuck-at fault models are insufficient for detecting faults and defects within cells. Conventional stuck-at/ transition test methods as well as the slow-speed or gross-delay cell-aware approaches cannot detect all cell-internal bridge defects. Thus, we had to move from using inter-cell fault models to intra-cell fault models. We found that the quality of test patterns improved significantly by explicitly targeting cell-internal bridge defects.
Stuck-at patterns also are insufficient to detect all detectable cell-internal bridge defects. Our previous experiments showed that only about 50% of today's standard library cells are guaranteed to be tested sufficiently with stuck-at patterns.
Recently, we conducted an analysis that compared the number of pattern sets needed for a gate-exhaustive pattern set in relation to a cell-aware pattern set. We evaluated the needed pattern sets to reach the maximum achievable coverage when applying the gate-exhaustive and cell-aware fault model on 1,500 library cells of a 65-nm CMOS technology and on 10 industrial designs.
By Friedrich Hapke and Stefan Eichenberger. (Hapke is Director of Engineering Germany in Mentor Graphics Silicon-Test-Solution division: Eichenberger is a senior principal engineer at NXP Semiconductors, The Netherlands.)
This brief introduction has been excerpted from the original copyrighted article.
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