Page loading . . .

 You are at: The item(s) you requested.Sunday, October 23, 2016
FPGA Functional Verification: Why Bother?  
Publication: Electronics Weekly
Contributor: Cadence Design Systems, Inc.
 Printer friendly
 E-Mail Item URL

October 11, 2011 -- FPGA engineers are all doing functional verification using manual processes but growing system comlexity is the issue. Changing tools and methodologies may seem daunting, but there is a way to break the problemn of verification down into achievable steps.

Every FPGA engineer does functional verification, but the tools are typically manual. The process begins with a verification plan with a list of tests to be conducted on each feature. The engineer will either write the HDL code or receive it from the designer or IP vendor. From that point, some short tests will be created to make sure each block of code can correctly process simple stimulus and each signal interface is correctly connected.

Typically, this is the point at which the FPGA engineer declares simulation done and enters the "burn-and-churn" cycle, where the functional verification occurs in most FPGA projects.

These functional tests often take the form of short software sequences or bench tests that directly test specific functions of the FPGA design. If an error is found, the FPGA probes can be reset to new nodes, the design can be recompiled, and the bug search continues until the issue is discovered, the code is changed, and the cycle is checked again for correctness.

This process works well when the input to the questionable code is easily controllable from the physical inputs and the code can be easily observed (probed) inside the programmed FPGA. When either or both condition is difficult, finding the bug is like hunting for a needle in a haystack in the dark.

By Adam Sherer. (Shere is Product Marketing Director at Cadence Design Systems, Inc.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the Electronics Weekly website.

Read more about
Cadence Design Systems, Inc.

Keywords: FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, functional verification, Cadence Design Systems, Electronics Weekly
599/35287 10/11/2011 1448 308
Designer's Mall

Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
and receive news, article, whitepaper, and product updates bi-weekly.


Verification Contortions

Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

Drilling Down on the Internet of Things

Ramesh Dewangan
VP Product Strategy
Real Intent, Inc.

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
DSP Design
Analog Design
Digital Design
Mixed-Signal Design
RF Design
EDA Tool Development

IC Packaging
PCB Design
RTOS Development
RTL Design
SystemC Design
SystemVerilog Design
Verilog Design
VHDL Design

Post a Job
Only $100 for 30 days

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts


Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.28125