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FPGA Functional Verification: Why Bother?  
Publication: Electronics Weekly
Contributor: Cadence Design Systems, Inc.
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October 11, 2011 -- FPGA engineers are all doing functional verification using manual processes but growing system comlexity is the issue. Changing tools and methodologies may seem daunting, but there is a way to break the problemn of verification down into achievable steps.

Every FPGA engineer does functional verification, but the tools are typically manual. The process begins with a verification plan with a list of tests to be conducted on each feature. The engineer will either write the HDL code or receive it from the designer or IP vendor. From that point, some short tests will be created to make sure each block of code can correctly process simple stimulus and each signal interface is correctly connected.

Typically, this is the point at which the FPGA engineer declares simulation done and enters the "burn-and-churn" cycle, where the functional verification occurs in most FPGA projects.

These functional tests often take the form of short software sequences or bench tests that directly test specific functions of the FPGA design. If an error is found, the FPGA probes can be reset to new nodes, the design can be recompiled, and the bug search continues until the issue is discovered, the code is changed, and the cycle is checked again for correctness.

This process works well when the input to the questionable code is easily controllable from the physical inputs and the code can be easily observed (probed) inside the programmed FPGA. When either or both condition is difficult, finding the bug is like hunting for a needle in a haystack in the dark.

By Adam Sherer. (Shere is Product Marketing Director at Cadence Design Systems, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Electronics Weekly website.

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Keywords: FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, functional verification, Cadence Design Systems, Electronics Weekly
599/35287 10/11/2011 887 108
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