December 19, 2011 -- Mentor Graphics Corp. today announced the availability of a set of protocol transactors for use with the Veloce hardware-emulation platform. The Veloce transactors enable the use of stimuli generated by modern simulation testbenches, including SystemVerilog/ OVM and UVM, SystemC, and C-based environments, and apply them to the design-under-test (DUT) running in the Veloce hardware. This allows engineers to stress-test a DUT that includes one or more protocol interfaces on their SOCs at orders of magnitude faster than simulation. Since the connection between the testbench and the Veloce transactors are at a transaction-level, rather than signal interface, a high level of performance is achieved.

The Veloce transactors provide protocol solutions for ARM's AMBA AXI, AHB, and APB standards, Universal Serial Bus (USB), PCI Express, Serial Attached SCSI (SAS), SPI, I2C, and audio standards including I2S. The ability to use the same testbench in both simulation and emulation leverages testbench development across the two platforms and accelerates design regression testing by hundreds of times over simulation.

The Veloce transactors are used as an essential part of the strategy for verifying SOCs containing multiple protocol interfaces on chip. Users can develop testbenches in one of several supported high-level verification (HVL) environments, and then seamlessly interchange between simulation and acceleration. This delivers an effective and productive environment to develop new, leading-edge SOCs and accelerates delivery schedules.

The Veloce transactors can be used with both transaction-based acceleration and traditional in-circuit emulation (ICE) modes of operation. The ability to mix and match ICE mode with high-performance transaction-based acceleration demonstrates the Veloce product's key benefit as a software-configurable verification platform.

Availability