November 13, 2003 -- As the electronics industry enters the less-than-100-nm-transistor era, delay sensitivity has also begun to venture into the picosecond range. You can also infer this high degree of timing accuracy by Moore's Law, which predicts that the density of on-chip transistors will double every 1.5 years. This increase in density has a direct effect on capacitance and other parameters, thus decreasing the delays of on-chip elements.
New methods are available for achieving a specific delay, such as DACEA (differential autocancellation of error architecture); other methods handle skew balancing, skew insertion, and delay characterization, all of which are useful in designing timing-critical circuits (Reference 1). Both methods are compatible with standard cell libraries, and proper layout can ensure that silicon results are close to the desired accuracy. The methods are technology-independent, thus allowing easy portability of the design into subsequent process generations. They are especially useful for classes of circuits that can compromise on silicon area to achieve picosecond-level accuracy.
By Naveen Tiwari and Ruchir Saraswat. (Tiwari and Ruchir Saraswat are design engineers at STMicroelectronics.)
This brief introduction has been excerpted from the original copyrighted article.