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Critical Area Analysis and Memory Redundancy  
Publication: EE Times EDA Designline
Contributor: Mentor Graphics Corp.
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December 19, 2011 -- Whether you are fabless, fab-lite, or IDM, the goal of reducing a design's sensitivity to manufacturing issues should ideally be handled by the design teams. The farther downstream a design goes, the less likely a manufacturing problem can be addressed without costly redesign. By addressing design-for-manufacturing (DFM) problems early, when the design is still in progress, manufacturing ramp-up issues can be avoided.

One aspect of DFM is determining how sensitive a physical design (layout) is to random particle defects. The probability of a random particle defect is a function of the spacing of layout features, so tighter spacing increases random defects. Because memories are relatively dense structures, they are inherently more sensitive to random defects, so when they are embedded in an SOC design, they can impact the overall yield of the device.

By Simon Favre. (Favre is a technical marketing engineer in the Mentor Graphics Corp. Calibre division.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

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Mentor Graphics Corp.
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Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, design for manufacturing, design-for-manufacturing, DFM, EE Times EDA Designline, Mentor Graphics
599/37162 12/19/2011 1089 82


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