You are at: The item(s) you requested.

Tuesday, May 21, 2013

Avery Design Systems Announces MIPI UniPro and UFS Verification Solution

January 12, 2012 -- Avery Design Systems, Inc. today announced the MIPI-Xactor verification solution supporting the MIPI UniPro and M-PHY, and JEDEC UFS specifications. MIPI-Xactor is a complete verification solution consisting of SystemVerilog UVM/ OVM/ VMM-compliant bus functional models (BFM), protocol checkers, directed and random compliance test suites, and reference verification frameworks. The MIPI-Xactor allows design and verification engineers to quickly and extensively test the functionality of UFS and UniPro/ M-PHY compliant host and device controller-based designs.

Key features

UFS Host

Emulates host driver and host controller.
Supports UFS DME and CPort users.
Supports command sets.
- Native UFS.
- SCSI SPC-4, SBC-3, SAM-5.

UniPro Core

Emulates UniPro protocol stack layers and M-PHY.
Supports all service primitives (SAP) and service data units (x_SDU).
DME User supports all sequences of control, configuration, and status primitives.
Transport service.
- Allocates connections between CPorts.
- Schedules message transfers between CPort users.
Supports CPort signal interface.
Supports UniPro test feature.

M-PHY

Multiple LANE provisions.
LS-MODE and HS_MODE.
LS-MODE NRZ and PWM signalling schemes.
Multiple power-saving modes.

Key BFM features

Layered environment based on family of SystemVerilog classes and methods.
Abstract data model for transfer, packet, and descriptor types.
Drivers, event callbacks, and scoreboard options automate status and result checking.
Robust error injection enables modifying, adding, or deleting frames.
UFS and UniPro transaction trackers (command and packet exchanges).
Throughput calculation for performance analysis.
Random scenario generation with constraints stress design operation.
Directed tests for focused functional compliance testing including UFS and SCSI commands and UFS and UniPro power modes.
Functional coverage monitoring of scenario cases.
Comprehensive protocol checking.
VMM/UVM/OVM support.

Go to the Avery Design Systems, Inc. website to find additional information.

E-mail Avery Design Systems, Inc. for more information.

Read more about
Avery Design Systems, Inc.
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, MIPI-Xactor verification, Avery Design Systems, SystemVerilog, Open Verification Methodology, OVM, Universal Verification Methodology, UVM, Verification Methodology Manual, VMM,

601/37357 1/13/2012 574 77

Designer's Mall

0.390625

Search site for:
Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP

Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship

Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!

Mike Donlin
The Write Solution
Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL

Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search
SOC Design ASIC Design ASIC Verification FPGA Design CPLD Design PCB Design DSP Design RTOS Development Digital Design	Analog Design Mixed-Signal Design DFT DFM IC Packaging VHDL Verilog SystemC SystemVerilog