January 16, 2012 -- Three-dimensional integrated circuit (3D-IC) systems offer the potential to deliver significant improvements in performance, power, functional density, and form factor over other packaging integration techniques. Despite substantial progress toward realizing 3D-IC systems, a variety of design, manufacturing, packaging, and testing issues still need to be addressed before cost-effective, high-volume production can be achieved. In this article we focus on the test challenges and solutions, highlighting a design-for-3D-test architecture and implementation flow developed by researchers at Industrial Technology Research Institute (ITRI) based on the Synopsys test solution.

By Chris Allsup, Adam Cron, Chen-An Chen, and Yee-Wen Chen. (Allsup is a marketing manager in Synopsys, Inc.'s synthesis and test group; Cron is a principal engineer and part of the test automation corporate applications engineering team at Synopsys; Chen-An Chen is deputy engineer for the design automation technology division at ITRI; Yee-Wen Chen is a technical deputy manager for the design automation technology division at ITRI.)