| Successful Adoption of DFM | Publication: EE Times EDA Designline Contributor: Mentor Graphics Corp.
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February 6, 2012 -- By now, the challenges of production at advanced process geometries are well-known. Even though EDA companies and foundries have been developing and perfecting design for manufacturing (DFM) technology for many years now, in anticipation of their customers' critical needs, many designers viewed DFM tools with skepticism as they continued to get products to market without them.
However, two factors are now influencing the use of DFM for IC development at 28nm and below. First, foundries now require or strongly recommend DFM checks for advanced nodes, essentially equating them to traditional design rule checks. This requirement implies a shift in responsibility; customers not running DFM checks during design verification may find the foundry less willing to address yield issues when the product goes into volume production. Second, some companies have discovered that DFM can be a source of competitive advantage, and are aggressively deploying it to wring more performance out of and/or increase reliability of their designs at leading-edge process nodes.
By Mark Redford and Jean-Marie Brunet. (Redford is currently the General Manager of North American Operations and Vice President of Advanced Process Technology Development at Cambridge Silicon Radio and Brunet is the Director of Product Marketing for Model-Based DFM and Place-and-Route Integration at Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
Read more about Mentor Graphics Corp. on SOCcentral.com |
| | Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, design for manufacturing, design-for-manufacturing, DFM, EE Times EDA Designline, Mentor Graphics
| | 602/37778 2/6/2012 789 112 | |
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| | 0.15625 |
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