Page loading . . .

  
 You are at: The item(s) you requested.Saturday, May 18, 2013
Successful Adoption of DFM  
Publication: EE Times EDA Designline
Contributor: Mentor Graphics Corp.
 Printer friendly
 E-Mail Item URL

February 6, 2012 -- By now, the challenges of production at advanced process geometries are well-known. Even though EDA companies and foundries have been developing and perfecting design for manufacturing (DFM) technology for many years now, in anticipation of their customers' critical needs, many designers viewed DFM tools with skepticism as they continued to get products to market without them.

However, two factors are now influencing the use of DFM for IC development at 28nm and below. First, foundries now require or strongly recommend DFM checks for advanced nodes, essentially equating them to traditional design rule checks. This requirement implies a shift in responsibility; customers not running DFM checks during design verification may find the foundry less willing to address yield issues when the product goes into volume production. Second, some companies have discovered that DFM can be a source of competitive advantage, and are aggressively deploying it to wring more performance out of and/or increase reliability of their designs at leading-edge process nodes.

By Mark Redford and Jean-Marie Brunet. (Redford is currently the General Manager of North American Operations and Vice President of Advanced Process Technology Development at Cambridge Silicon Radio and Brunet is the Director of Product Marketing for Model-Based DFM and Place-and-Route Integration at Mentor Graphics Corp.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
Mentor Graphics Corp.
on SOCcentral.com

Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, design for manufacturing, design-for-manufacturing, DFM, EE Times EDA Designline, Mentor Graphics
602/37778 2/6/2012 789 112


Designer's Mall
0.15625



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.25