February 16, 2012 -- Verific Design Automation, Inc. has been selected by Blue Pearl Software, Inc. to support its Blue Pearl Software Suite. The Blue Pearl Software Suite is register transfer level (RTL) analysis software used by FPGA and ASIC designers. Verific's SystemVerilog and VHDL parsers and RTL elaborator have been integrated with Blue Pearl's software used for comprehensive RTL analysis, clock-domain crossing checks (CDCs) and automatic Synopsys Design Constraints (SDC) constraint generation.

"It was logical to us to choose Verific Design Automation for the 6.0 version of the Blue Pearl Software Suite since Verific is an instantly recognizable brand-name provider of Verilog, SystemVerilog and VHDL parsers," remarks Scott Aron Bloom, Blue Pearl's Director of Product Development.