March 8, 2012 -- Mentor Graphics Corp. today announced that a new flow developed for GlobalFoundries by the Mentor Consulting Division (MCD) using the Calibre suite of tools has demonstrated the ability to improve incoming design yield.
A silicon experiment performed by GlobalFoundries and Mentor resulted in a significant yield increase on a test chip after the integrated flow made automatic design-for-manufacturing (DFM) improvements using multiple Calibre tools for analysis and direct modification to the GDS layout database. The flow, which is available to GlobalFoundries customers for 45/40- and 32/28-nm processes, features rapid turn-around time for full-chip designs, maintains design-performance specifications, and helps ensure that the results are DRC clean by immediately verifying all changes during the modification process.
"We are extremely pleased with the work that MCD has done to engineer a flow customized for GlobalFoundries that helps us easily and quickly make DFM improvements to our customers' designs, which will boost yield without impacting performance or introducing DRC errors," said Luigi Capodieci, Director of DFM/CAD and R&D fellow at GlobalFoundries. "We also like that the flow is highly modular and scalable, which allows us to easily move it to new processes and to extend it to address additional DFM issues as we uncover new design-based yield limiters."
The new GlobalFoundries flow is a result of an engagement under MCD's Yield Enhancement Services (YES) offering. The Mentor engineers worked directly with GlobalFoundries engineers to understand their exact requirements and to build a solution that takes maximum advantage of the integrated Calibre tool suite. The flow quickly filters the design database to identify areas that require DFM improvement, to apply needed enhancements, and immediately recheck the modified layout to ensure that the changes do not introduce DRC violations or other issues.
The flow employs the Calibre nmDRC, Calibre YieldAnalyzer, and Calibre YieldEnhancer tools to automatically perform metal widening, via doubling, and via enclosure improvements, including support for rectangular vias. These modifications have resulted in significant increases in silicon yield. Because the analysis is done very efficiently and operates directly on the GDS database, turn-around time is fast, even for complex full-chip designs.
Results were validated by direct comparison of test silicon with the Mentor test and yield analysis tools, including Tessent TestKompress, Tessent Diagnosis and Tessent YieldInsight. Test failures were traced back to layout locations and the root cause was determined using physical failure analysis to correlate the failures to specific design-based limiters that could be eliminated using DFM enhancements. The GlobalFoundries solution is user friendly, letting its customers select and deselect specific enhancements through a simple user interface. It is also easily adaptable to new technologies and process nodes. For example, the flow was ported from 32/28nm to 45/40nm in a matter of a few days.
Go to the Mentor Graphics Corp. website to find additional information.