March 6, 2012 -- This article describes the idea of generating synthesizable IP core by a software tool taking an error correction algorithm of BCH (Bose-Chaudhuri-Hocquenghem) as an example. First, it gives an overview on the challenges associated with the error correction module flexibility being a trigger to study the subject. It is followed by a short introduction of NAND Flash memory and Error Correction Codes (ECC) supplemented by BCH algorithm description. In the next chapters specific implementation details are provided accompanied by highlights of configuration parameters and procedure conducted to generate selected architecture of module. Finally, the article concludes giving a very simple example how the application takes full set of parameters and translate it into the RTL source code.
By Michal Jedrak, Filip Rak and Tomasz Wojciechowski. (Jedrak and Wojciechowski are with Evatronix SA; Rak is at the Warsaw University of Technology.)
This brief introduction has been excerpted from the original copyrighted article.
