Page loading . . .

 You are at: The item(s) you requested.Saturday, October 22, 2016
Density Requirements at 28nm  
Publication: EE Times EDA Designline
Contributor: Mentor Graphics Corp.
 Printer friendly
 E-Mail Item URL

March 12, 2012 -- In recent discussions with customers around the world, we have been hearing a surprising new message; that, at 28nm, they have to care about density at the cell-design level "like never before." It's surprising because density has historically been a manufacturing issue that was handled post tape-out or during chip assembly. However, where and how density is handled in the design process has evolved significantly along with the process technologies.

In this article, I'll take a look at how density has evolved from a back-end manufacturing issue that was of little interest to designers to a design concern that affects the layout of standard cell libraries.

By Joe Davis. (Davis is Product Manager for Calibre interactive and integration products at Mentor Graphics Corp.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the EE Times EDA Designline website.

Read more about
Mentor Graphics Corp.

Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, standard cells, EE Times EDA Designline, Mentor Graphics
602/38189 3/12/2012 920 210
Designer's Mall

Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
and receive news, article, whitepaper, and product updates bi-weekly.


Verification Contortions

Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

Drilling Down on the Internet of Things

Ramesh Dewangan
VP Product Strategy
Real Intent, Inc.

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
DSP Design
Analog Design
Digital Design
Mixed-Signal Design
RF Design
EDA Tool Development

IC Packaging
PCB Design
RTOS Development
RTL Design
SystemC Design
SystemVerilog Design
Verilog Design
VHDL Design

Post a Job
Only $100 for 30 days

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts


Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.3125