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Density Requirements at 28nm  
Publication: EE Times EDA Designline
Contributor: Mentor Graphics Corp.
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March 12, 2012 -- In recent discussions with customers around the world, we have been hearing a surprising new message; that, at 28nm, they have to care about density at the cell-design level "like never before." It's surprising because density has historically been a manufacturing issue that was handled post tape-out or during chip assembly. However, where and how density is handled in the design process has evolved significantly along with the process technologies.

In this article, I'll take a look at how density has evolved from a back-end manufacturing issue that was of little interest to designers to a design concern that affects the layout of standard cell libraries.

By Joe Davis. (Davis is Product Manager for Calibre interactive and integration products at Mentor Graphics Corp.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the EE Times EDA Designline website.

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Mentor Graphics Corp.

Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, standard cells, EE Times EDA Designline, Mentor Graphics
602/38189 3/12/2012 744 144
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