April 2, 2012 -- Synopsys, Inc. today announced availability of the latest release of its Synplify Pro and Synplify Premier FPGA synthesis tools. The Synplify 2012.03 products include improved synthesis algorithms that accelerate runtime by up to 30%.

In addition, the Synplify Premier software is enhanced with a new continue-on-error feature to address FPGA designers' need for fast turn-around time by enabling them to generate a report and fix all errors resulting from missing or incorrect design definitions at the end of the hardware description language (HDL) compilation step rather than incrementally fixing an error and rerunning the compile step. This capability is especially important with SOC prototypers who may not be intimately familiar with the HDL code they have to implement in an FPGA. Also, the new Synplify Premier software release further automates the process of building high reliability and fault tolerance into an FPGA design using a combination of advanced features including selective triple-modular redundancy (TMR), fault-tolerant error-correcting code (ECC) memories and Hamming-3 encoding for detection and correction of soft errors.

"The run-time improvement in Synopsys' Synplify products combined with the compile time advantage we have in our Quartus II software provide our mutual customers a productivity edge that allows them to reduce overall implementation time when designing for our latest 28-nm FPGAs,"said Alex Grbic, Director of Marketing for software, DSP and IP at Altera.

The new Synplify 2012.03 software release offers FPGA designers significantly shorter design cycles. The continue-on-error feature addresses FPGA-based prototypers' need for fast turn-around time by eliminating the need to address errors one at a time as they are found during HDL compilation. It is especially useful for FPGA-based prototypers who may not be as familiar with the source HDL code. Instead of stopping with each error, the tool continues compilation after an error is found, generating a report of all the errors encountered so that they can be addressed at once, without re-compiling between each fix. To further simplify the process for ASIC prototypers, the Synplify synthesis tool has a datapath latch-conversion feature to automatically convert an ASIC design to an FPGA implementation, making it possible for the designer to use a single set of source files to implement the FPGA-based prototype. Users of Synopsys' Certify multi-FPGA prototyping environment also benefit from the streamlined error-handling and conversion features in the new Synplify software, which helps speed the validation process and reduce development time.

The latest release of the Synplify Premier software enhances its support for high reliability by giving designers the ability to address radiation effects such as single-event upsets (SEUs) through multiple error-mitigation techniques including localized and selective TMR implementation. In addition, the Synplify Premier software can infer error-correcting memory and automatically make the proper connections to take advantage of ECC memories offered by FPGA vendors. The latest release also supports fault-tolerant finite-state machine (FSM) implementation using Hamming-3 encoding to automatically detect and correct single-bit errors that might occur in the registers of an FSM.

"Rapid bring-up of a new design is critical for design teams trying to meet tight market windows. And Synopsys synthesis technology can reduce the number of design iterations and provide diagnostic information sooner," said Ed Bard, Senior Director of Marketing of the Solutions Group at Synopsys. "With the combination of improved algorithms that deliver faster run-times and the new continue-on-error feature and hierarchical design techniques, FPGA-based prototypers and FPGA designers alike can significantly reduce the time required to get working implementations of their designs while continuing to see the high quality of results they expect from Synplify tools."

Availability