April 25, 2012 -- Power seems to be the buzzword for 2012. Of course, it always has been important but, for some reason, it seems to be even more important now. Of course, it always has been important but, for some reason, it seems to be even more important now. Why is that?
Traditionally the power problem has been attacked from two sides. First, the chip or system architect would make architectural trade-offs based on past experiences with limited practical data in hopes of getting the higher order bits correct. Then, in register transfer level (RTL) code and below, design and implementation teams would do their best to squeeze out milliwatts while carefully managing the area, performance, power QoR triangle. This was and is a careful balancing act at best, sometimes with disastrous results.
Ultimately, there are two issues with the above process. At the architectural level, it is much easier (relatively speaking) to make design changes quickly that may have a significant impact on power. However, there is little data about how the chip/ system will react once implemented for each of these design changes because the abstraction level is too high. Of course, with the actual RTL code, this isn't as much of a problem because the detail is there. Making design changes that can significantly impact power in RTL code is generally not possible without changing the architecture, which would take too much time. Even small micro-architecture changes can take a long time in RTL code and do not generally have a significant power benefit.
Chip designers need a way to get better data earlier in the process without committing to specific architectural choices and the RTL code until much later in the process. Further, the RTL code needs to produce a high quality of results across multiple dimensions.
This is where high-level synthesis (HLS) can help. HLS has been known for its ability to raise the abstraction level as compared to RTL with better results (area) in less time. Could HLS be applied to the power problem? The answer is yes.
By Brett Cline. (Cline is Vice President of Marketing and Sales at Forte Design Systems, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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