April 13, 2012 -- Not too long ago, low-power design was an esoteric discipline practiced mostly by makers of digital watches and calculators. In the last 20 years, a steady series of new products that run on batteries for much of their lives has brought the need for power conservation to the forefront of the electronics business. Cell phones, smart phones, tablets, and other consumer devices have sophisticated, power-hungry processors and wireless links. Further, "green" laws and industry initiatives have mandated lower power even for "big iron" servers, switches, and telephony equipment.
At the heart of all these products are system-on-chip (SOC) designs combining one or more embedded processors with a variety of functional units, all interconnected by some type of bus or fabric. There is a wide range of techniques used to reduce the power consumed by these SOCs, including innovative transistor and cell designs, substrate biasing, and varying voltages. These have no significant effect on verification of the system model or the RTL design. However, the technique that has the highest impact on verification is perhaps the most widely used: power shut-off (PSO).
While simple in concept, PSO has many tricky aspects in implementation that must be carefully verified. For example, it may be necessary to save some of the state (registers or memory) in a powered-down unit. All of these implementation details must be verified using the RTL design, and preferably on the system-level model first. The implications of PSO reach all the way up to the system architect, who needs to determine which units can be safely powered-down, and under what circumstances.
By Thomas L. Anderson. (Anderson is Vice President of Marketing for Breker Verification Systems, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Electronic Engineering Times (EE Times) website.
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