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GlobalFoundries Fab 8 Adds Tools to Enable 3D Chip Stacking at 20nm and Beyond  
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April 30, 2012 -- At its Fab 8 campus in Saratoga County, New York, GlobalFoundries has begun installation of a special set of production tools to create through-silicon vias (TSVs) in semiconductor wafers processed on the company's leading-edge 20-nm technology platform.

At leading-edge nodes, the adoption of 3D stacking of integrated circuits is increasingly being viewed as an alternative to traditional technology-node scaling at the transistor level. However, as new packaging technologies are introduced, the complexity of chip-package interaction is going up significantly and it is increasingly difficult for foundries and their partners to be able to deliver end-to-end solutions that meet the requirements of the broad range of leading-edge designs.

"To help address these challenges on new silicon nodes, we are engaging early with partners to jointly develop packaging solutions that will enable the next wave of innovation in the industry," said Gregg Bartlett, Chief Technology Officer of GlobalFoundries. "Our approach is broad and collaborative, giving customers maximum choice and flexibility, while delivering cost savings, faster time-to-volume, and a reduction in the technical risk associated with developing new technologies. With the installation of TSV capabilities for 20-nm technology in Fab 8, we are adding an important capability that will be supplemented by our joint development and manufacturing partnerships with companies across the semiconductor ecosystem, from design to assembly and test."

The first full-flow silicon with TSVs is expected to start running at Fab 8 in Q3 2012.



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Keywords: ASICs, ASIC design, 3D ICs, 3D chips, stacked ICs, foundries, foundry services, GlobalFoundries
601/38349 4/30/2012 1434 99


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