May 9, 2012 -- Excellicon today announced it adopted Verific Design Automation, Inc.'s industry-standard, IEEE-compliant front-end platform for use with its software for timing constraints authoring, verification and management.

The Verific SystemVerilog and VHDL parsers and register transfer level (RTL) elaborator have been tightly integrated with Excellicon's Timing Constraints Compiler. Excellicon's products are targeted at solving complexity associated with latest requirements in timing constraints, including multi-mode constraints generation, verification and management, as well as full mode analysis capabilities. They will be demonstrated during DAC in Booth #610 June 4-6 at the Moscone Center in San Francisco.

"Selecting Verific's front-end software enabled us to focus on our core competency and get our products to market much faster," remarked Peter Petrov, founder and CEO of Excellicon. "Its reputation for quality, reliable software and excellent support is well earned. The Verific team should be commended for its customer support and service."

Excellicon's ConMan Constraints Manager is based on patented formal technology targeted at solving complex problems facing chip designers, from initial planning through final timing closure where implementation expertise is needed. Its tools provide the infrastructure to develop, track, optimize and verify information for the entire design for faster time to tape-out. They also enable designers to seamlessly propagate constraints for any mode in the design to any layer of hierarchy with ease.

Verific will offer demonstrations of its RTL front-end solutions in DAC Booth #1807. In addition, its software will be demonstrated in 20 other DAC exhibitor booths.