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JEDEC Announces Publication of LPDDR3 Standard for Low-Power Memory Devices  
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May 17, 2012 -- JEDEC today announced the publication of JESD209-3 LPDDR3 Low Power Memory Device Standard, designed to satisfy the performance and memory-density demands of the latest generation of mobile devices such as smartphones, tablets, ultra-thin notebooks and similar connected devices on the newest, high-speed 4G networks.

LPDDR3 offers a higher data rate, improved bandwidth and power efficiency, and higher memory densities over its predecessor, LPDDR2. Developed by JEDEC's JC-42.6 Subcommittee for Low Power Memories, the LPDDR3 Low Power Memory Device Standard is available for free download from the JEDEC website.

LPDDR3 achieves a data rate of 1600Mbps (versus 1066Mbps for LPDDR2) through the addition of new features, including:

  • Write-leveling and CA training - These features allow the memory controller to compensate for signal skew, ensuring that data-input setup-and-hold timing as well as command and address-input timing requirements are met while operating at the industry's fastest input bus speeds.
  • On-die termination (ODT) - This optional feature enables a light termination to LPDDR3 data lanes to improve high-speed signaling with minimal impact on power consumption, system operation and pin count.
  • Low I/O capacitance.

As with LPDDR2, LPDDR3 supports both package-on-package and discrete packaging types in order to meet the requirements of a wide array of mobile devices, offering designers the ability to select the options that best meet the needs of their products. LPDDR3 will preserve the power-efficient features and signaling interface of LPDDR2, allowing for fast clock stop/ start, low-power self-refresh, and smart array management.

"To help address the dramatic rise in data-intensive apps and the resulting demands on device memory, JEDEC LPDDR3 is designed to focus on higher bandwidth requirements for device processors and graphic units," said Hung Vuong, Chairman of JC-42.6. "LPDDR3 represents countless hours of collaboration within the JC-42.6 Subcommittee, and was developed rapidly in order to meet the mobile industry's bandwidth requirements."



Go to the JEDEC website for details.

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Keywords: ASICs, ASIC design, computer system design, general-purpose computers, special-purpose computers, embedded system design, embedded systems, low power design, low-power design, IP, intellectual property, cores, LPDDR3 memory, JEDEC,
601/38482 5/17/2012 395 53


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