December 12, 2011-- Formal analysis, also known as property checking, has made significant progress in the last ten years in terms of ease of use, speed, capacity, and assertion-language standardization. Formal analysis has demonstrated clear value as an important component in the functional verification of both intellectual property (IP) and system-on-chip (SOC) designs. It complements RTL lint checking, simulation, simulation acceleration, in-circuit emulation (ICE), equivalence checking, and other verification techniques that are more widely adopted.

This is the first in a series of three articles presenting the "top 10" tips for the successful use of formal analysis. These tips are based on more than a dozen years of experience with this technology, including most of the leading commercial formal products. The tips presume very little knowledge of formal tools or the assertions that drive them, and are discussed at a level of detail appropriate for both new users and current users looking for more advantage from their tools. Verification leads and project managers can also benefit from many of these tips.

By Thomas Anderson. (Anderson is Verification Product Management Group Director, Cadence Design Systems, Inc.)