June 4, 2012 -- Aldec, Inc. earlier this year announced the availability of Open Source-VHDL Verification Methodology (OS-VVM), delivering advanced verification test methodologies to VHDL design engineers. Once again underscoring its commitment to provide continued support to the VHDL design community, Aldec will host the OS-VVM community's first User Group Meeting at the Design Automation Conference.

The OS-VVM User Group Meeting will be held on Monday, June 4, 2:00pm–3:00pm. The presenters are Jim Lewis, Synthworks (creator of the original OS-VVM packages) and Jerry Kaczynski, Aldec Research Engineer.

The agenda

About OS-VVM

OS-VVM is an intelligent testbench methodology that allows mixing of "Intelligent Coverage" (coverage driven randomization) with directed, algorithmic, file-based, and constrained random test approaches. The methodology can be adopted in part or in whole as needed. OS-VVM lets users add advanced verification methodologies to current testbenches without having to learn a new language or discard existing testbenches or testbench models.