June 4, 2012 -- A new electronic design automation (EDA) company and a new product were launched at DAC 2012. Ausdia, Inc. delivers a comprehensive timing-constraints development, verification and management solution that complements all implementation and timing sign-off flows.Ausdia's Timevision integrates with all aspects of the design flow and is used before synthesis, before DFT insertion, before place-and-route, and when sign-off timing is being run. Timevision helps designers create good SDC/TCL constraints and is a verification platform for existing timing constraints. The company's technology represents a new way for system-on-chip (SOC) and IC developers to make massive productivity gains across the design flow.

Using multicore software design, patent-pending analysis algorithms, and innovative formal verification technology, Timevision was built specifically to handle very large, complex SOC designs (especially above 50M gates).

Timevision delivers run times that are 3X to 10X faster than static timing analysis (STA) tools, a standard benchmark when evaluating constraint-verification technologies. Ausdia technology also overcomes the problem of huge amounts of "static analysis noise," which can make diagnosis a time-consuming problem. Timevision delivers concise summary outputs that can progressively be expanded, rather than being overwhelming from the start. The company also has developed a solution to help designers find their most complex "timing relief" optimizations towards the tail end of the chip design process using high-performance formal-analysis techniques.

"In our experience, timing constraints are the most common cause for timing closure to fail or to take too long, and it's usually realized far too late in the design process, causing significant impact to tape-out schedules," said Sam Appleton, President and CEO of Ausdia. "If the timing constraints for a complex design are bad, it either won't close timing or will come back from the foundry not working. Timing-constraint development requires an integrated, high-performance solution like Timevision, especially for any design team working with large, complex SOCs or IPs."

More about Timevision

Timevision represents a new way for STA engineers to massively increase their productivity, by operating as constraint synthesizers, rather than line-by-line writers and debuggers. Timevision also integrates a variety of formal, structural and simulation-based technologies to aid STA engineers in the quick and confident development of constraints from high-level data.

Timevision brings this same capability to RTL designers, who are often under more pressure to be involved with timing closure (but lack the time available to dive into gate-level issues), and to implementation engineers trying to make sense of constraints and how best to implement their designs (but lack the detailed knowledge of the design).

Timevision is based on a standard TCL shell, so the integration and user interface is easily understood by anyone who has used STA or synthesis tools. Run times measure in minutes, so constraints can be checked rapidly, in real time, without waiting for multi-hour runs. The platform also handles every variant of multi-language designs — Verilog, gate, SystemVerilog and all VHDL variants — allowing all designs that will read into a synthesis tool to be read into Timevision, with almost no change to the scripting flow.

Availability and Pricing

Timevision is available now. U.S. pricing for a yearly base package starts at $125,000 per license.