June 27, 2012 -- Synopsys, Inc. and the Semiconductor Manufacturing International Corp. (SMIC) today announced availability of version 5.0 of their 40-nm RTL-to-GDSII reference design flow. This production-proven flow incorporates a range of automated low-power and high-performance capabilities through Synopsys' entire tool suite.
The reference flow is the result of collaboration between SMIC and Synopsys Professional Services. The reference flow features new high-performance design techniques, including automated clock-mesh synthesis, to increase performance and responsiveness of a system-on-chip (SOC), plus a gate array engineering-change-order (ECO) flow that allows a designer to quickly achieve design closure without having to start from scratch with a redesign. The reference flow also includes support for low-power techniques such as power-aware clock tree synthesis, power gating and physical optimization, driven by the IEEE 1801 low-power design-intent standard.
The SMIC-Synopsys Reference Flow 5.0 is available now.