| Software Extends Hardware-in-the-Loop Real-Time Simulation | Publication: EE Times Automotive Designline
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June 25, 2012 -- Somewhat similar to automotive development, in the space industry the design, building and testing of planetary rover prototypes is extremely expensive, and system testing typically does not occur until late in the design/ testing process, leading to a long, protracted development time.
In response to such timing issues, Amir Khajepour, Canada Research Chair in Mechatronic Vehicle Systems and engineering professor in the Mechanical and Mechatronics Engineering department at the University of Waterloo (Canada), and his team worked with the Canadian Space Agency (CSA) and Maplesoft, to develop a hardware-in-the-loop (HIL) test platform for solar-powered planetary rovers.
By Tina George. (George is with Maplesoft.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Automotive Designline website.
| | Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, timing analysis, timing optimization, timing closure, EE Times Automotive Designline
| | 602/38800 6/25/2012 528 89 | |
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| | 0.15625 |
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