July 10, 2012 -- Synopsys, Inc. and the Semiconductor Manufacturing International Corp. (SMIC) today announced the availability of a broad set of Synopsys DesignWare IP on the SMIC 40-nm low-leakage (40LL) process. The SMIC 40LL process technology combines advanced immersion lithography, strain engineering, ultra-shallow junction and ultra-low-k dielectric to deliver the optimized power and performance required of mobile multimedia and consumer devices.

Synopsys DesignWare IP available now or scheduled to be available later this year on the SMIC 40LL process includes:

"Our collaboration with Synopsys offers designers targeting the consumer market a proven path to a wide range of technology-leading IP on advanced process nodes," said Chris Chi, Chief Business Officer at SMIC. "Our first-pass silicon success with Synopsys' DesignWare USB, HDMI and audio codec IP, where all critical performance metrics meet or exceed the target specifications, demonstrates the stability and maturity of SMIC's 40LL technology."

Availability

DesignWare USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5-Gbps/ 3-Gbps PHY, SATA 6-Gbps PHY, and select audio codecs and data converter IP are available now from Synopsys on the SMIC 40LL process. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and embedded memory and logic library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.